//Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
//--------------------------------------------------------------------------------
//Tool Version: Vivado v.2019.2 (win64) Build 2708876 Wed Nov  6 21:40:23 MST 2019
//Date        : Tue Nov 26 15:22:27 2024
//Host        : Laptop-LZY running 64-bit major release  (build 9200)
//Command     : generate_target dds.bd
//Design      : dds
//Purpose     : IP block netlist
//--------------------------------------------------------------------------------
`timescale 1 ps / 1 ps

(* CORE_GENERATION_INFO = "dds,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=dds,x_ipVersion=1.00.a,x_ipLanguage=VERILOG,numBlks=2,numReposBlks=2,numNonXlnxBlks=0,numHierBlks=0,maxHierDepth=0,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=0,numPkgbdBlks=0,bdsource=USER,synth_mode=OOC_per_IP}" *) (* HW_HANDOFF = "dds.hwdef" *) 
module dds
   (CLK,
    Q);
  (* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLK.CLK CLK" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME CLK.CLK, CLK_DOMAIN dds_CLK_0, FREQ_HZ 10000000, INSERT_VIP 0, PHASE 0.000" *) input CLK;
  output [7:0]Q;

  wire CLK_0_1;
  wire [5:0]address_Q;
  wire [7:0]sin_rom_douta;

  assign CLK_0_1 = CLK;
  assign Q[7:0] = sin_rom_douta;
  dds_c_counter_binary_0_0 address
       (.CLK(CLK_0_1),
        .Q(address_Q));
  dds_blk_mem_gen_0_1 sin_rom
       (.addra(address_Q),
        .clka(CLK_0_1),
        .douta(sin_rom_douta));
endmodule
